1. Field of the Invention
The present invention relates to a fully integrable phase locked loop (PLL) particularly suited for applications that require an increased short term stability (low jitter).
The invention is particularly useful for generating a programmable reference frequency in order to maintain a constant density of data stored in the read/write "channels" of hard disks, or for implementing a phase separation of data (data separator PLL), or the like.
2. Discussion of Related Art
The functional block diagram of a phase locked loop (PLL) is depicted in FIG. 1.
Basically, the circuit includes a phase detector 10 for monitoring the phase difference between two signals, a charge pump circuit 12, a low pass loop filter 14, a voltage controlled oscillator (VCO) 16, and a phase control feedback network (1/N COUNTER) 18.
An analysis of the frequency characteristic of a PLL such as that shown in FIG. 1 may be based on the corresponding linear block diagram depicted in FIG. 2.
In the above mentioned applications, the transfer function F(s) of the low pass loop filter 14 is commonly of the following type: ##EQU1## corresponding to the transfer function of a passive network, such as that shown in FIG. 3, which is often constructed outside the integrated circuit.
Referring to FIG. 3, the capacitances C1, which are functionally connected between the two nodes 34 and 36 of the low pass filter and a common ground node 38 of the circuit, introduce a third pole in the transfer function of the PLL. By an appropriate sizing, for example C.apprxeq.10C.sub.1, the transfer function of the low pass loop filter may be simplified as follows: ##EQU2##
By taking into account the above simplified expression, the open loop transfer function of the entire PLL may be written as follows: ##EQU3##
The open loop gain characteristic of such a PLL, from which stability and ability to respond to eventual phase errors may be analyzed, is shown in FIG. 4. The presence of the third pole p.sub.3 generated by the capacitances C1 is clearly recognizable in the diagram of FIG. 4.
As may be observed from the diagram of FIG. 4, the position of the zero 1/.tau. and of the third pole p.sub.3 markedly condition the functioning of the PLL system.
It should be noted also, especially for the type of application mentioned above, that .omega..sub.0 should be adjustable while, at the same time, the damping factor .xi. should be kept constant.
In order to satisfy this important requirement, 1/.tau. and p.sub.3 should be sufficiently spaced from each other in the frequency domain in order to ensure a damping factor .xi. of sufficient value (typically not less than 0.707).
On the other hand, the position of the pole p.sub.3 should not be excessively distant from 1/.tau. because the loop must retain a good rejection capability of high frequency disturbances in order to optimize the short term stability characteristic (minimize jitter).
In known circuits, it is difficult to reconcile these contrasting requirements in an optimum way and, generally, these conditions imply a definite limitation on the circuit's ability to minimize jitter. This is extremely critical when the capacitances are external to the chip because of the presence of noise coming from the supply rails on the metal frame on which the chip is mounted. On the other hand, even in known circuits made in a completely integrated form, the ability to appropriately filter high frequency disturbances remains limited.